The speeds of metal-oxide-semiconductor (MOS) transistors are closely related to the drive currents of the MOS transistors, which drive currents are further closely related to the mobility of charges. For example, NMOS transistors have high drive currents when the electron mobility in their channel regions is high, while PMOS transistors have high drive currents when the hole mobility in their channel regions is high.
Compound semiconductor materials of group III and group V elements (commonly known as III-V compound semiconductors) are good candidates for forming NMOS transistors for their high electron mobility. Therefore, III-V compound semiconductors have been used to form NMOS transistors. To reduce the manufacturing cost, methods for forming PMOS transistors using III-V compound semiconductors have also been explored. FIG. 1 illustrates a conventional transistor incorporating III-V compound semiconductors. In the formation process, a plurality of layers is blanket formed on a silicon substrate, wherein the plurality of layers includes a buffer layer formed of GaAs, a graded buffer formed of InxAl1-xAs (with x between, but not equal to, 0 and 1), a bottom barrier formed of In0.52Al0.48As, a channel formed of In0.7Ga0.3As, a top barrier formed of In0.52Al0.48As, an etch stop layer formed of InP, and a contact layer formed of In0.53Ga0.47As. A first etch is performed to etch through the contact layer stopping at the etch stop layer to form a first recess. A second etch is then performed to etch through the etch stop layer, and etch into a portion of the top barrier to form a second recess. A gate, which is formed of metal, is then formed in the second recess. The resulting transistor has the advantageous features resulting from the quantum well being formed of the bottom barrier, the channel, and the top barrier.
The above-described structure and process steps, however, suffer from process difficulties. To have good short-channel controllability, distance Tins between the gate and the channel needs to be carefully controlled, which requires that etching depth D be accurately controlled. However, accurately controlling etching depth D is difficult. Particularly, it is difficult to achieve uniform etching depth D throughout the respective chip. It is realized that at the time the second recess is formed, a plurality of recesses is formed simultaneously for forming other transistors. However, distance Tins of the plurality of recesses at different locations of a chip/wafer may be different, resulting in non-uniformity in the performance of the resulting transistors. A method and structure for overcoming the above-described shortcomings in the prior art are thus needed.